1. Field of the Invention
The present invention relates to a multi-power supply integrated circuit employing multiple power supply voltages and, more particularly, a multi-power supply integrated circuit capable of reducing a chip area without reduction in reliability and a circuit system employing such multi-power supply integrated circuit.
2. Description of the Background Art
It is more difficult to design all the semiconductor integrated circuit manually as the semiconductor integrated circuit becomes larger in scale. Hence, a semicustom design methodology which is an automated design by using a computer has been commonly employed. This semicustom design methodology means such an approach that a plurality of standard basic circuits (logic cells) are prepared in advance and then a desired circuit is developed by carrying out an automatic design of these logic cells with the use of the computer aided design. As typical examples of such semicustom design methodology, there are a gate array design approach and a standard array design approach. For the purposes of example, in the gate array approach shown in FIG. 1, basic cells 103 used to constitute basic logic circuits such as NAND, NOR, NOT are aligned regularly in rows on a semiconductor chip 101, and wiring passages (wiring channels) 107 used to connect the basic cells 103 to each other are provided between respective cell arrays 105. Therefore, a target circuit can be developed in a short time only by installing wirings between the desired basic cells 103 via the wiring channels 107. For example, as shown in FIG. 2A, the basic cells 103 are composed of source/drain regions 74, 75, 76, 77 and polysilicon regions 71 to constitute a plurality of PMOS transistors (abbreviated to "pMOSs" hereinafter) and a plurality of nMOS transistors (abbreviated to "nMOSs" hereinafter). Then, as shown in FIG. 2B, basic logic circuits can be formed by installing the wirings to connect these transistors.
In FIG. 2A, two neighboring basic cells 103 are depicted as a basic cell 103a and a basic cell 103b. The basic cells 103a, 103b are composed of p.sup.+ source/drain diffusion regions 74, 75, n.sup.+ source/drain diffusion regions 76, 77, and gate polysilicon regions 71 respectively. In other words, in FIG. 2A, two basic cells 103a, 103b each of which is composed of two nMOSs 1a, 1b and two pMOSs 2a, 2b are placed so as to put substrate contact regions 78, 79 therebetween respectively, thus constituting one functional block. In a layout according to the gate array approach, as shown in FIG. 2A, a wiring channel lattice serving as a criterion in designing wiring layers is provided on a surface including the basic cells 103a, 103b. Along the wiring channel lattice consisting of twelve lines X0 to X11 depicted in the X direction and seven lines Y0 to Y6 depicted in the Y direction, the overall layout of metal wirings, contact holes and via holes etc. would be designed. FIG. 2B shows layout patterns of the metal wirings if a four-input NAND circuit shown in FIG. 2C is constituted in the layout of the gate basic cell shown in FIG. 2A, to which the wiring channel lattice is provided. By disposing vertical metal wirings (i.e., VDD power supply wiring 85a and VSS power supply wiring 85b) and lateral metal wirings (interconnections 86) to connect the transistors 1a, 1b, 2a, 2b mutually, the four-input (A, B, C, D) NAND gate (Z output) can be completed.
A low power consumption requirement is made much account more and more with the progress of an integration density of the semiconductor integrated circuit. Rapidly increasing demand for portable electronic products has prompted a great deal of interest in integrated circuits with very low power consumption. Lower power consumption can be achieved in principle if amplitudes of the supply voltages are made smaller. And the most common approach for reducing power consumption in integrated circuits is to lower the supply voltage. However, a speed-performance of the integrated circuit becomes degraded if the supply voltages are uniformly decreased. Since various logic circuits and gates are included in the semiconductor integrated circuit, basic cells which need a high speed operation and basic cells which do not need relatively the high speed operation are often formed mixedly on a semiconductor chip. Therefore, in the event that the cells and the gates for which the high speed operation is required are driven by the high supply voltage (V.sub.DDH) ensuring the peak performance of transistors and circuits while the cells and the gates for which the high speed operation is not required so much are driven by the low supply voltage (V.sub.DDL), low power consumption of the semiconductor integrated circuit can be achieved while keeping the high speed operation as an overall performance.
According to such design concept, the inventors of the present invention have examined the multi-power supply integrated circuit. However, it has been found by the inventors of the present invention that, if the multi-power supply integrated circuit employing multiple supply voltages (e.g., two supply voltages consisting of the high supply voltage (V.sub.DDH) and the low supply voltage (V.sub.DDL)) is designed, such a disadvantage is caused that a chip area is increased rather than the case where a single supply voltage is employed, as will be explained later.
FIG. 3 is a sectional view showing a part of a gate array having integrated circuits operating with two supply voltages, which has been examined as a preliminary stage of the present invention. As shown in FIG. 3, in this multi-power supply integrated circuit, a PMOS 3 which constitutes a high potential basic cell (V.sub.DDH cell) operated at the high supply voltage (V.sub.DDH) and a pMOS 115 which constitutes a low potential basic cell (V.sub.DDL cell) operated at the low supply voltage (V.sub.DDL) are placed adjacently on a p substrate 1 to sandwich a boundary line 111 of the high potential basic cell and the low potential basic cell therebetween. The PMOS 3 comprises a gate electrode 71 serving as a gate, a p.sup.+ diffusion layer 75 formed in an n-well 73 and serving as a drain, a p.sup.+ diffusion layer 74 formed in the n-well 73 and serving as a source, and an n.sup.+ diffusion layer 78 for supplying the high supply voltage (V.sub.DDH) to the n-well 73. Similarly, the pMOS 115 comprises a gate electrode 17 serving as a gate, a p.sup.+ diffusion layer 19 formed in an n-well 133 and serving as a drain, a p.sup.+ diffusion layer 131 formed in the n-well 133 and serving as a source, and an n.sup.+ diffusion layer 135 for supplying the low supply voltage (V.sub.DDL) to the n-well 133. Usually, in the CMOS circuit, the source region and "the substrate" (or the p-well if the nMOS is formed in the p-well) of the nMOS is connected to ground (GND), and the source region and "the substrate" (or the n-well if the pMOS is formed in the n-well) of the PMOS are connected to the supply voltage (VDD). Therefore, the PMOS 3 operated at the high supply voltage and the pMOS 115 operated at the low supply voltage must be formed in different n-wells respectively. For this reason, as described above, the pMOS 3 and the pMOS 115 are formed separately in the n-wells 73, 133, and then the high supply voltage (V.sub.DDH) is applied to the n-well 73 in which the pMOS 3 is formed while the low supply voltage (V.sub.DDL) is applied to the n-well 133 in which the pMOS 115 is formed. Consequently a high voltage of (V.sub.DDH -V.sub.DDL) is applied to an region located between the n-well 73 and the n-well 133, and therefore carrier injection from the n-well 73 to the n-well 133 is caused through an area indicated by A in FIG. 3 if a resistance between two n-wells is small. This carrier injection causes reduction in reliability of the integrated circuit.
In order to suppress such carrier injection, as shown in FIG. 4, an approach has been thought out wherein the basic cell 103H composed of the pMOS 3 operated at the high supply voltage and the basic cell 103L composed of the pMOS 115 operated at the low supply voltage are placed to be separated at a certain distance so as to obtain high resistance between two n-wells. But, as shown in FIG. 4, this arrangement is substantially equivalent to formation of basic cells 103H', 103L' which correspond to the basic cells 103H, 103L expanded in the lateral direction (i.e., direction indicated by an arrow in FIG. 4). This causes an increase of the chip area of the semiconductor chip 101. In order to avoid such increase of the chip area as illustrated in FIG. 4, another approach may be thought out wherein a common n-well for high supply voltage and another common n-well for low supply voltage are provided so that two common n-wells are separated by a predetermined distance each other. And a cell array consisting of a plurality of high potential basic cells and another cell array consisting of a plurality of low potential basic cells are arranged in respective common n-wells. In this case, lengths of the wiring provided between individual basic cells which are formed in one common n-well and individual basic cells which are formed in another common n-well are made longer. A wiring space is increased correspondingly if the number of wiring is increased. Also, longer wirings cause the problem of signal delay due to the wirings.
As has mentioned earlier, it has been derived from the inventors' examination that, if the multi-power supply integrated circuit is designed according to the above-mentioned semicustom design methodology, the basic cells which are operated at different supply voltages have to be arranged separately at a distance to assure reliability in operation of the integrated circuit, so that the increase of the chip area is inevitably brought about.